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5-46 Operating Registers
SSM Single Step Mode 4
Setting this bit causes the LSI53C810A to stop after
executing each SCRIPTS instruction, and generate a
single step interrupt. When this bit is cleared the
LSI53C810A does not stop after each instruction. It
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit clear. To restart the LSI53C810A
after it generates a SCRIPTS Step interrupt, read the
Interrupt Status (ISTAT) and DMA Status (DSTAT)
registers to recognize and clear the interrupt. Then set
the START DMA bit in this register.
IRQM IRQ Mode 3
When set, this bit enables a totem pole driver for the IRQ
pin. When reset, this bit enables an open drain driver for
the IRQ pin with a internal weak pull-up. This bit is reset
at power-up.
STD Start DMA Operation 2
The LSI53C810A fetches a SCSI SCRIPTS instruction
from the address contained in the DMA SCRIPTS Pointer
(DSP) register when this bit is set. This bit is required if
the LSI53C810A is in one of the following modes:
• Manual start mode – Bit 0 in the DMA Mode
(DMODE) register is set
• Single step mode – Bit 4 in the DMA Control (DCNTL)
register is set
When the LSI53C810A is executing SCRIPTS in manual
start mode, the Start DMA bit needs to be set to start
instruction fetches. This bit remains set until an interrupt
occurs. When the LSI53C810A is in single step mode, set
the Start DMA bit to restart execution of SCRIPTS after
a single step interrupt.
IRQD IRQ Disable 1
Setting this bit 3-states the IRQ pin. Clearing the bit
enables normal operation. When bit 1 in this register is
set, the IRQ/ pin is not asserted when an interrupt
condition occurs. The interrupt is not lost or ignored, but
merely masked at the pin. Clearing this bit when an
interrupt is pending immediately causes the IRQ/ pin to