Filter
Top Products
5-31
SIGP Signal Process 6
This bit is a copy of the SIGP bit in the Interrupt Status
(ISTAT) register (bit 5). The SIGP bit is used to signal a
running SCRIPTS instruction. When this register is read,
the SIGP bit in the Interrupt Status (ISTAT) register is
cleared.
CIO Configured as I/O 5
This bit is defined as the Configuration I/O Enable Status
bit. This read only bit indicates if the chip is currently
enabled as I/O space.
Note: Both bits 4 and 5 may be set if the chip is dual-mapped.
CM Configured as Memory 4
This bit is defined as the configuration memory enable
status bit. This read only bit indicates if the chip is
currently enabled as memory space.
Note: Both bits 4 and 5 may be set if the chip is dual-mapped.
R Reserved 3
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C810A’s internal
TEOP signal. The TEOP signal acknowledges the
completion of a transfer through the SCSI portion of the
LSI53C810A. When this bit is set, TEOP is active. When
this bit is clear, TEOP is inactive.
DREQ Data Request Status 1
This bit indicates the status of the LSI53C810A’s internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is clear, DREQ is inactive.
DACK Data Acknowledge Status 0
This bit indicates the status of the LSI53C810A’s internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is clear, DACK/ is active.