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R Reserved 2
EXT Extend SREQ/SACK Filtering 1
LSI Logic TolerANT SCSI receiver technology includes a
special digital filter on the SREQ/ and SACK/ pins which
causes the disregarding of glitches on deasserting
edges. Setting this bit increases the filtering period from
30 ns to 60 ns on the deasserting edge of the SREQ/ and
SACK/ signals.
Note: Never set this bit during fast SCSI (greater than
5 megatransfers per second) operations, because a valid
assertion could be treated as a glitch.
LOW SCSI Low level Mode 0
Setting this bit places the LSI53C810A in low level mode.
In this mode, no DMA operations occur, and no SCRIPTS
execute. Arbitration and selection may be performed by
setting the start sequence bit as described in the SCSI
Control Zero (SCNTL0) register. SCSI bus transfers are
performed by manually asserting and polling SCSI
signals. Clearing this bit allows instructions to be
executed in SCSI SCRIPTS mode.
Note: It is not necessary to set this bit for access to the SCSI
bit-level registers (SCSI Output Data Latch (SODL), SCSI
Bus Control Lines (SBCL), and input registers.
Register: 0x4F (0xCF)
SCSI Test Three (STEST3)
Read/Write
TE TolerANT Enable 7
Setting this bit enables the active negation portion of
TolerANT technology. Active negation causes the SCSI
Request, Acknowledge, Data, and Parity signals to be
actively deasserted, instead of relying on external
pull-ups, when the LSI53C810A is driving these signals.
Active deassertion of these signals occurs only when the
76543210
TE STR HSC DSI R TTM CSF STW
0000x000