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5-28 Operating Registers
also notify the LSI53C810A of a predefined condition and
the SCRIPTS processor may take action while SCRIPTS
are executing.
CON Connected 3
This bit is automatically set any time the LSI53C810A is
connected to the SCSI bus as an initiator or as a target.
It is set after successfully completing selection or when
the LSI53C810A responds to a bus-initiated selection or
reselection. It is also set after the LSI53C810A wins
arbitration when operating in low level mode. When this
bit is clear, the LSI53C810A is not connected to the SCSI
bus.
INTF Interrupt-on-the-Fly 2
This bit is asserted by an INTFLY instruction during
SCRIPTS execution. SCRIPTS programs do not halt
when the interrupt occurs. This bit can be used to notify
a service routine, running on the main processor while
the SCRIPTS processor is still executing a SCRIPTS
program. If this bit is set when the Interrupt Status
(ISTAT) register is read it is not automatically cleared. To
clear this bit, write it to a one. The reset operation is
self-clearing.
Note: If the INTF bit is set but SIP or DIP is not set, do not
attempt to read the other chip status registers. An
Interrupt-on-the-Fly interrupt must be cleared before
servicing any other interrupts indicated by SIP or DIP.
This bit must be written to one in order to clear it after it
has been set.
SIP SCSI Interrupt Pending 1
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C810A. The
following conditions cause a SCSI interrupt to occur:
• A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
• An arbitration sequence completes
• A selection or reselection time-out occurs
• The LSI53C810A is selected
• The LSI53C810A is reselected