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6-18 Instruction Set of the I/O Processor
field stored in the DMA Next Address (DNAD) register.
Manually set the LSI53C810A to Initiator mode if it is
reselected, or to Target mode if it is selected.
4. If the Select with SATN/ field is set, the SATN/ signal
is asserted during the selection phase.
Wait Disconnect Instruction
1. The LSI53C810A waits for the Target to perform a
“legal” disconnect from the SCSI bus. A “legal”
disconnect occurs when SBSY/ and SSEL/ are
inactive for a minimum of one Bus Free delay
(400 ns), after the LSI53C810A has received a
Disconnect Message or a Command Complete
Message.
Wait Reselect Instruction
1. If the LSI53C810A is selected before being
reselected, it fetches the next instruction from the
address pointed to by the 32-bit jump address field
stored in the DMA Next Address (DNAD) register.
Manually set the LSI53C810A to Target mode when it
is selected.
2. If the LSI53C810A is reselected, it fetches the next
instruction from the address pointed to by the DMA
SCRIPTS Pointer (DSP) register.
3. If the CPU sets the SIGP bit in the Interrupt Status
(ISTAT) register, the LSI53C810A aborts the Wait
Reselect instruction and fetches the next instruction
from the address pointed to by the 32-bit jump
address field stored in the DMA Next Address (DNAD)
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the SCSI Output Control Latch
(SOCL) register are set. When the target bit is set, the
corresponding bit in the SCSI Control Zero (SCNTL0)
register is also set. When the Carry bit is set, the
corresponding bit in the ALU is set.