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PCI Cache Mode 3-3
3.1.2.3 Memory Read Command
The Memory Read reads data from an agent mapped in memory
address space. All 32 address bits are decoded.
3.1.2.4 Memory Read Multiple Command
The Memory Read Multiple command reads data from an agent mapped
in memory address space. All 32 address bits are decoded.
3.1.2.5 Memory Read Line Command
The Memory Read Line command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
3.1.2.6 Memory Write Command
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
3.1.2.7 Memory Write and Invalidate Command
The Memory Write and Invalidate command writes data to an agent
when mapped in memory address space. All 32 address bits are
decoded.
3.2 PCI Cache Mode
The LSI53C810A supports the PCI specification for an 8-bit Cache Line
Size register located in PCI configuration space. The Cache Line Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the Cache
Line Size register, the PCI commands Read Line, Read Multiple, and
Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands.
3.2.1 Support for PCI Cache Line Size Register
The LSI3C810A supports the PCI specification for an 8-bit Cache Line
Size register in PCI configuration space. It can sense and react to
nonaligned addresses corresponding to cache line boundaries.