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2-6 Functional Description
Table 2.1 Bits Used for Parity Control and Observation
BIt Name Location Description
Assert SATN/ on Parity
Errors
SCSI Control
Zero (SCNTL0),
Bit 1
Causes the LSI53C810A to automatically assert SATN/
when it detects a parity error while operating as an
initiator.
Enable Parity Checking SCSI Control
Zero (SCNTL0),
Bit 3
Enables the LSI53C810A to check for parity errors.
The LSI53C810A checks for odd parity.
Assert Even SCSI Parity SCSI Control
One (SCNTL1),
Bit 2
Determines the SCSI parity sense generated by the
LSI53C810A to the SCSI bus.
Disable Halt on SATN/ or
a Parity Error (Target
Mode Only)
SCSI Control
One (SCNTL1),
Bit 5
Causes the LSI53C810A not to halt operations when a
parity error is detected in target mode.
Enable Parity Error
Interrupt
SCSI Interrupt
Enable Zero
(SIEN0), Bit 0
Determines whether the LSI53C810A generates an
interrupt when it detects a SCSI parity error.
Parity Error SCSI Interrupt
Status Zero
(SIST0), Bit 0
This status bit is set whenever the LSI53C810A
detects a parity error on the SCSI bus.
Status of SCSI Parity
Signal
SCSI StatusZero
(SSTAT0), Bit 0
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
Latched SCSI Parity SCSI Status One
(SSTAT1), Bit 3
This bit reflects the SCSI odd parity signal
corresponding to the data latched into the SCSI Input
Data Latch (SIDL) register.
Master Parity Error
Enable
Chip Test Four
(CTEST4), Bit 3
Enables parity checking during master data phases.
Master Data Parity Error DMA Status
(DSTAT), Bit 6
Set when the LSI53C810A, as a PCI master, detects a
target device signaling a parity error during a data
phase.
Master Data Parity Error
Interrupt Enable
DMA Interrupt
Enable (DIEN),
Bit 6
By clearing this bit, a Master Data Parity Error does not
cause assertion of IRQ/, but the status bit is set in the
DMA Status (DSTAT) register.