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Interrupt Handling 2-21
• If the DMA direction is a write to memory and a SCSI interrupt
occurs, the LSI53C810A attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
should be checked to see if any data remains in the DMA FIFO.
• SCSI SREQ/SACK handshakes that have begun are completed
before halting.
• The LSI53C810A attempts to clean up any outstanding synchronous
offset before halting.
• In the case of Transfer Control Instructions, once instruction
execution begins it continues to completion before halting.
• If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA
SCRIPTS Pointer (DSP) is updated to the transfer address before
halting.
• All other instructions may halt before completion.
2.7.1.6 Sample Interrupt Service Routine
The following is a sample of an interrupt service routine for the
LSI53C810A. It can be repeated during polling or should be called when
the IRQ/ pin is asserted if hardware interrupts.
1. Read Interrupt Status (ISTAT).
2. If the INTF bit is set, it must be written to a one to clear this status.
3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and
SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt
condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupt(s) occurred and determine what
action is required to service the interrupt(s).
4. If only the DIP bit is set, read the DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in
DSTAT tell which DMA interrupts occurred and determine what action
is required to service the interrupts.
5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero
(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the
interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 CLK delay between the