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6-38 Instruction Set of the I/O Processor
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address
(DSA) registers are additional holding registers used during the Memory
Move. However, the contents of the Data Structure Address (DSA)
register are preserved.
6.7.1 First Dword
IT[1:0] Instruction Type - Memory Move Instruction [31:30]
R Reserved [29:25]
These bits are reserved and must be zero. If any of these
bits is set, an illegal instruction interrupt occurs.
NF No Flush 24
When this bit is set, the LSI53C810A performs a Memory
Move (MMOV) without flushing the prefetch unit
(NFMMOV). When this bit is cleared, the Memory Move
instruction automatically flushes the prefetch unit. Use
the NFMMOV if the source and destination are not within
four instructions of the current MMOV instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
TC[23:0] Transfer Count [23:0]
The number of bytes to transfer is stored in the lower 24
bits of the first instruction word.
6.7.2 Second Dword
DSPS Register [31:0]
These bits contain the source address of the Memory
Move.
6.7.3 Third Dword
TEMP Register [31:0]
These bits contain the destination address for the
Memory Move.