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5-52 Operating Registers
SEL Selected 5
This bit is set when the LSI53C810A is selected by
another SCSI device. The Enable Response to Selection
bit must be set in the SCSI Chip ID (SCID) register (and
the Response ID (RESPID) register must hold the chip’s
ID) for the LSI53C810A to respond to selection attempts.
RSL Reselected 4
This bit is set when the LSI53C810A is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the SCSI Chip ID (SCID)
register (and the Response ID (RESPID) register must
hold the chip’s ID) for the LSI53C810A to respond to
reselection attempts.
SGE SCSI Gross Error 3
This bit is set when the LSI53C810A encounters a SCSI
Gross Error Condition. The following conditions can result
in a SCSI Gross Error Condition:
• Data Underflow – reading the SCSI FIFO register
when no data is present.
• Data Overflow – writing too many bytes to the SCSI
FIFO, or the synchronous offset causes overwriting
the SCSI FIFO.
• Offset Underflow – the LSI53C810A is operating in
target mode and a SACK/ pulse is received when the
outstanding offset is zero.
• Offset Overflow – the other SCSI device sends a
SREQ/ or SACK/ pulse with data which exceeds the
maximum synchronous offset defined by the SCSI
Transfer (SXFER) register.
• A phase change occurs with an outstanding
synchronous offset when the LSI53C810A is
operating as an initiator.
• Residual data in the synchronous data FIFO – a
transfer other than synchronous data receive is
started with data left in the synchronous data FIFO.
UDC Unexpected Disconnect 2
This bit is set when the LSI53C810A is operating in the
initiator mode and the target device unexpectedly
disconnects from the SCSI bus. This bit is only valid