Filter
Top Products
5-26 Operating Registers
Registers:0x10–0x13 (0x90–0x93)
Data Structure Address (DSA)
Read/Write
DSA Data Structure Address [31:0]
This 32-bit register contains the base address used for all
table indirect calculations. The DSA register is usually
loaded prior to starting an I/O, but it is possible for a
SCRIPTS Memory Move to load the DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
Register: 0x14 (0x94)
Interrupt Status (ISTAT)
Read/Write
This register is accessible by the host CPU while a LSI53C810A is
executing SCRIPTS (without interfering in the operation of the function).
It is used to poll for interrupts if hardware interrupts are disabled. Read
this register after servicing an interrupt to check for stacked interrupts.
For more information on interrupt handling refer to Chapter 2, “Functional
Description.”
ABRT Abort Operation 7
Setting this bit aborts the current operation being
executed by the LSI53C810A. If this bit is set and an
interrupt is received, clear this bit before reading the DMA
Status (DSTAT) register to prevent further aborted
interrupts from being generated. The sequence to abort
any operation is:
1. Set this bit.
2. Wait for an interrupt.
31 0
DSA[31:0]
00000000000000000000000000000000
76543210
ABRT SRST SIGP SEM CON INTF SIP DIP
00000000