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Interrupt Handling 2-15
Figure 2.4 Determining the Synchronous Transfer Rate
2.7 Interrupt Handling
The SCRIPTS processor in the LSI53C810A performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C810A.
2.7.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
SCLK
SCF
Divider
CCF
Divider
Synchronous
Divider
Asynchronous
SCSI Logic
Divide by 4
SCF2 SCF1 SCF0 SCF
Divisor
0011
0 1 0 1.5
0112
1003
0003
TP2 TP1 TP0 XFERP
Divisor
0004
0015
0106
0117
1008
1019
11010
11111
CCF2 CCF1 CCF0 SCSI Clock (MHz)
0 0 0 50.1-66.00
0 0 1 16.67-25.00
0 1 0 25.01-37.50
0 1 1 37.51-50.00
1 0 0 50.01-66.00
Example:
SCLK = 40 MHz, SCF = 1 (/1), XFERP = 0 (/4),
CCF = 3(37.51-50.00 MHz)
This point
must not
exceed
50 MHz
Receive
Clock
Send Clock
(to SCSI Bus)
This point
must not
exceed
25 MHz
= (40/1) /4 = 10 Mbytes/s
Synchronous receive rate = (SCLK/SCF) /4 =
(40/1) /4 = 10 Mbytes/s
Synchronous send rate = (SCLK/SCF) /XFERP