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LSI53C810A PCI to SCSI I/O Processor 3-1
Chapter 3
PCI Functional
Description
Chapter 3 is divided into the following sections:
• Section 3.1, “PCI Addressing”
• Section 3.2, “PCI Cache Mode”
• Section 3.3, “Configuration Registers”
3.1 PCI Addressing
There are three types of PCI-defined address space:
• Configuration space
• Memory space
• I/O space
3.1.1 Configuration Space
Configuration space is a contiguous 256-byte set of addresses dedicated
to each “slot” or “stub” on the bus. Decoding C_BE/[3:0] determines if a
PCI cycle is intended to access the configuration register space. The
IDSEL bus signal is a chip select that allows access to the configuration
register space only. Any attempt to access configuration space is ignored
unless IDSEL is asserted. The eight lower order address lines and byte
enables select a specific 8-bit register. The host processor uses this
configuration space to initialize the LSI53C810A.
The lower 128 bytes of the LSI53C810A configuration space hold system
parameters while the upper 128 bytes map into the LSI53C810A
operating registers. For all PCI cycles except configuration cycles, the
LSI53C810A registers are located on the 256-byte block boundary
defined by the base address assigned through the configured register.