LSI 53C810A Computer Hardware User Manual


 
Load and Store Instructions 6-39
6.7.4 Read/Write System Memory from a SCRIPTS Instruction
By using the Memory Move instruction, single or multiple register values
may be transferred to or from system memory.
Because the LSI53C810A responds to addresses as defined in the Base
Address Zero (I/O) or Base Address One (Memory) registers, it can be
accessed during a Memory Move operation if the source or destination
address decodes to within the chip’s register space. If this occurs, the
register indicated by the lower seven bits of the address is taken to be
the data source or destination. In this way, register values are saved to
system memory and later restored, and SCRIPTS can make decisions
based on data values in system memory.
The SCSI First Byte Received (SFBR) is not writable using the CPU, and
therefore not by a Memory Move. However, it can be loaded using
SCRIPTS Read/Write operations. To load the SFBR with a byte stored
in system memory, first move the btye to an intermediate LSI53C810A
register (for example, a SCRATCH register), and then to the SFBR.
The same address alignment restrictions apply to register access
operations as to normal memory-to-memory transfers.
6.8 Load and Store Instructions
The Load and Store instruction provide a more efficient way to move data
from/to memory to/from an internal register in the chip without using the
normal memory move instruction.
The load and store instructions are represented by two Dword opcodes.
The first Dword contains the DMA Command (DCMD) and DMA Byte
Counter (DBC) register values. The second Dword contains the DMA
SCRIPTS Pointer Save (DSPS) value. This is either the actual memory
location of where to Load and Store, or the offset from the Data Structure
Address (DSA), depending on the value of bit 28 (DSA Relative).
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The destination memory address in the Store instruction and
the source address in the Load instruction may not map back to the