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PCI Cache Mode 3-5
3.2.3.2 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C810A enables Memory Write and Invalidate cycles
when bit 0 (WRIE) in the Chip Test Three (CTEST3) register and bit 4
(WIE) in the PCI Command register are set. When the following
conditions are met, Memory Write and Invalidate commands are issued:
• The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL))
register), WRIE bit (Write and Invalidate Enable, bit 0, Chip Test
Three (CTEST3) register, and PCI configuration Command register,
bit 4 are set.
• The Cache Line Size register contains a legal burst size (2, 4, 8 or
16) value AND that value is less than or equal to the DMA Mode
(DMODE) burst size.
• The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
• The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C810A issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – When multiple cache lines of data
have been read in during a MMOV instruction (see the description for the
Read Multiple command), the LSI53C810A issues a Write and Invalidate
command using the burst size necessary to transfer all the data in one
transfer. For example, if the cache line size is 4, and the chip read in
16 Dwords of data using a Read Multiple command, the chip switches
the burst size to 16, and issues a Write and Invalidate to transfer all
16 Dwords in one bus ownership.
Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out occurs, the LSI53C810A continues to transfer up until a
cache line boundary. At that point, the chip relinquishes the bus, and