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3-8 PCI Functional Description
When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is determined by the DMA Mode (DMODE) burst size bits. In
other words, the chip switches its normal operating burst size to reflect
the DMA Mode (DMODE) burst size settings for the Read Multiple
command. For example, if the cache line size is 4, and the DMA Mode
(DMODE) burst size is 16, the chip switches the current burst size from
4 to 16, and issues a Read Multiple. After the transfer, the chip switches
the burst size back to the normal operating burst size of 4.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
3.2.5 Unsupported PCI Commands
The LSI53C810A does not respond to reserved commands, special
cycle, dual address cycle, or interrupt acknowledge commands as a
slave. It never generates these commands as a master.
PCI bus commands and encoding types appear in Table 3.1.