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Index IX-3
I
I/O bit 5-25
I/O instructions 6-13
I_O bit 5-18
IARB bit 5-7
IDSEL 4-7
IID bit 5-22
, 5-44
illegal instruction detected bit 5-22
, 5-44
immediate arbitration bit 5-7
initialization device select 4-7
initiator mode
phase mismatch 5-51
initiator ready 4-7
input 4-3
instructions
block move 6-5
I/O 6-13
load and store 6-39
memory move 6-36
read/write 6-23
transfer control 6-27
interrupt
line 3-18
pin (IP[7:0]) 3-18
interrupt status register 5-26
interrupt-on-the-fly bit 5-28
interrupts
fatal vs. nonfatal interrupts 2-18
halting 2-20
IRQ disable bit 2-17
, 5-46
masking 2-18
polling vs. hardware 2-15
registers 2-16
stacked interrupts 2-19
INTF bit 5-28
IRDY/ 4-7
IRQ disable bit 5-46
IRQ mode bit 5-46
IRQD bit 5-46
IRQM bit 5-46
ISTAT register 5-26
L
last disconnect bit 5-25
latched SCSI parity bit 5-24
latency
timer (LT[7:0]) 3-16
LDSC bit 5-25
LOA bit 5-23
load and store instructions 6-39
no flush option 6-40
prefetch unit and store instructions 2-4
, 6-41
lost arbitration bit 5-23
LOW bit 5-63
LSI53C700 family compatibility bit 5-47
LSI53C810A
ease of use 1-4
flexibility 1-5
integration 1-4
performance 1-3
reliability 1-5
testability 1-6
M
M/A bit 5-48, 5-51
MACNTL register 5-55
MAN bit 5-43
manual start mode bit 5-43
MASR bit 5-37
master control for set or reset pulses bit 5-37
master data parity error bit 5-21
MDPE bit 5-44
master enable bit 5-56
master parity error enable bit 5-35
max SCSI synchronous offset bits 5-14
max_lat (ML[7:0]) 3-19
MDPE bit 5-21
memory access control register 5-55
memory move instructions 6-36
and SCRIPTS instruction prefetching 2-3
no flush option 6-38
memory read line command 3-6
memory read multiple command 3-7
memory write and invalidate command 3-5
write and invalidate mode bit 3-12
min_gnt (MG[7:0]) 3-19
move to/from SFBR cycles 6-24
MPEE bit 5-35
MSG bit 5-18
, 5-20, 5-25
N
NFMMOV instruction 6-38
no flush memory-to-memory move 6-38
O
OLF bit 5-23
opcode fetch bursting 2-4
operating registers
adder sum output 5-47
chip test five 5-36
chip test four 5-34
chip test one 5-30
chip test six 5-37
chip test three 5-32
chip test two 5-30
chip test zero 5-29
data structure address 5-26
DMA byte counter 5-38
DMA command 5-39
DMA control 5-45
DMA FIFO 5-33
DMA interrupt enable 5-44
DMA mode 5-41
DMA next address 5-39
DMA SCRIPTS pointer 5-39
DMA SCRIPTS pointer save 5-40
DMA status 5-20
general information 5-1
general purpose 5-16
general purpose pin control 5-56
interrupt status 5-26
memory access control 5-55
response ID zero 5-59
scratch register A 5-41
SCSI bus control lines 5-20