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2-14 Functional Description
2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])
The CCF[2:0] bits select the frequency of the SCLK for asynchronous
SCSI operations. To meet the SCSI timings as defined by the ANSI
specification, these bits need to be set properly.
2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0])
The TP[2:0] divider (XFERP) bits determine the SCSI synchronous send
rate in either initiator or target mode. This value further divides the output
from the SCF divider.
2.6.3.5 Achieving Optimal SCSI Send Rates
To achieve optimal synchronous SCSI send timings, the SCF divisor
value should be set high, to divide the clock as much as possible before
presenting the clock to the TP divider bits in the SCSI Transfer (SXFER)
register. The TP[2:0] divider value should be as low as possible. For
example, with 40 MHz clock to achieve a Mbytes/s send rate, the SCF
bits can be set to divide by 1 and the TP bits to divide by 8; or the SCF
bits can be set to divide by 2 and the TP bits set to divide by 4. Use the
second option to achieve optimal SCSI timings.