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LSI53C810A PCI to SCSI I/O Processor IX-1
Index
Symbols
(AD[31:0]) 4-6
(BARO[31:0]) 3-17
(BARZ[31:0]) 3-17
(CLS[7:0]) 3-16
(FMT) 5-29
(HT[7:0]) 3-17
(IL[7:0]) 3-18
(IP[7:0]) 3-18
(LT[7:0]) 3-16
(MG[7:0]) 3-19
(ML[7:0]) 3-19
Numerics
encoded chip SCSI ID, bits 5-12
3.3/5 volt PCI interface 2-5
3-state 4-3
A
AAP bit 5-5
abort operation bit 5-26
aborted bit 5-21
, 5-44
ABRT bit 5-21
, 5-26, 5-44
AC characteristics 7-10
ACK bit 5-18
, 5-20
ADB bit 5-6
ADCK bit 5-36
ADDER register 5-47
adder sum output register 5-47
AESP bit 5-7
AIP bit 5-23
ARB[1:0] bits 5-3
arbitration
arbitration mode bits 5-3
in progress bit 5-23
mode bits 5-3
priority encoder test bit 5-60
ART bit 5-60
assert even SCSI parity (force bad parity) bit 5-7
assert SATN/ on parity error bit 5-5
assert SCSI ACK bit 5-18
assert SCSI ATN/ bit 5-18
assert SCSI BSY/ bit 5-18
assert SCSI C_D/ bit 5-18
assert SCSI data bus bit 5-6
assert SCSI I_O/ bit 5-18
assert SCSI MSG/ bit 5-18
assert SCSI REQ/ signal bit 5-18
assert SCSI RST/ signal bit 5-7
assert SCSI SEL/ bit 5-18
ATN bit 5-18
, 5-20
B
base address register
one (BARO[31:0]) 3-17
zero - I/O (BARZ[31:0]) 3-17
BBCK bit 5-36
BDIS bit 5-34
benefits summary 1-3
BF bit 5-21
, 5-44
bidirectional 4-3
BL[1:0] bits 5-41
block move instructions 6-5
BO[6:0] bits 5-33
BOF bit 5-43
BSY bit 5-18
, 5-20
burst disable bit 5-34
burst length bits 5-41
burst mode fetch enable bit 5-43
bus command and byte enables 4-6
bus fault bit 5-21
, 5-44
byte
empty in DMA FIFO (FMT) 5-29
byte empty in DMA FIFO bits 5-30
byte full in DMA FIFO bits 5-30
byte offset counter bits 5-33
C
C_BE/[3:0] 4-6
C_D bit 5-18
, 5-20, 5-25
cache line size
(CLS[7:0]) 3-16
cache line size enable bit 5-45
cache mode, see PCI cache mode 3-3
CCF[2:0] bits 5-10
chip revision level bits 5-32
chip test five register 5-36
chip test four register 5-34
chip test one register 5-30
chip test six register 5-37
chip test two register 5-30
chip test zero register 5-29
chip type bits 5-55
CIO bit 5-31
clear SCSI FIFO bit 5-64
CLK 4-5
clock 4-5