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in the Interrupt Status (ISTAT) register is also cleared. It is possible to
mask DMA interrupt conditions individually through the DMA Interrupt
Enable (DIEN) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT),
SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure that the interrupts clear properly.
See Chapter 2, “Functional Description,” for more information on
interrupts.
DFE DMA FIFO Empty 7
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
MDPE Master Data Parity Error 6
This bit is set when the LSI53C810A as a master detects
a data parity error, or a target device signals a parity error
during a data phase. This bit is completely disabled by
the Master Parity Error Enable bit (bit 3 of Chip Test Four
(CTEST4)).
BF Bus Fault 5
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C810A is
bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
ABRT Aborted 4
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the Interrupt Status (ISTAT)
register.
SSI Single Step Interrupt 3
If the Single Step Mode bit in the DMA Control (DCNTL)
register is set, this bit is set and an interrupt is generated
after successful execution of each SCRIPTS instruction.
SIR SCRIPTS Interrupt Instruction Received 2
This status bit is set whenever an Interrupt instruction is
evaluated as true.