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PCI Interface Timing Diagrams 7-13
7.4.1 Target Timing
Figure 7.9 through Figure 7.12 describe target timing.
Figure 7.9 PCI Configuration Register Read
Data Out
Byte Enable
t
2
In
Out
t
1
t
2
t
1
t
3
t
2
t
1
t
1
t
2
t
2
t
3
t
3
t
2
t
1
t
3
t
2
t
1
CLK
(Driven by System)
FRAME/
(Driven by System)
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C810A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C810A)
STOP/
(Driven by LSI53C810A)
DEVSEL/
(Driven by LSI53C810A)
IDSEL
(Driven by Master)
CMD
Addr
In
AD/
(Driven by Master-Addr;
LSI53C810A-Data)