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5-50 Operating Registers
Register: 0x41 (0xC1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the SCSI Interrupt Status One
(SIST1) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, refer to Chapter 2, “Functional
Description.”
R Reserved [7:3]
STO Selection or Reselection Time-out 2
This bit controls whether an interrupt occurs when the
SCSI device which the LSI53C810A was attempting to
select or reselect did not respond within the programmed
time-out period. See the description of the SCSI Timer
Zero (STIME0) register bits [3:0] for more information on
the time-out timer.
GEN General Purpose Timer Expired 1
This bit controls whether an interrupt occurs when the
general purpose timer is expired. The time measured is
the time between enabling and disabling of the timer. See
the description of the SCSI Timer One (STIME1) register,
bits [3:0], for more information on the general purpose
timer.
HTH Handshake to Handshake timer Expired 0
This bit controls whether an interrupt occurs when the
handshake-to-handshake timer is expired. The time
measured is the SCSI Request-to-Request (target) or
Acknowledge-to-Acknowledge (initiator) period. See the
description of the SCSI Timer Zero (STIME0) register,
bits [7:4], for more information on the handshake-to-
handshake timer.
7 3210
R STO GEN HTH
x x x x x000