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5-64 Operating Registers
LSI53C810A is in an information transfer phase.
TolerANT active negation should be enabled to improve
setup and deassertion times at fast SCSI timings. Active
negation is disabled after reset or when this bit is cleared.
For more information on TolerANT technology, refer to
Chapter 1, “General Description.”
STR SCSI FIFO Test Read 6
Setting this bit places the SCSI core into a test mode in
which the SCSI FIFO is easily read. Reading the SCSI
Output Data Latch (SODL) register causes the FIFO to
unload.
HSC Halt SCSI Clock 5
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower I
DD
during a power-down
mode.
DSI Disable Single Initiator Response 4
If this bit is set, the LSI53C810A ignores all
bus-initiated selection attempts that employ the single
initiator option from SCSI-1. In order to select the
LSI53C810A while this bit is set, the LSI53C810A’s SCSI
ID and the initiator’s SCSI ID must both be asserted.
Assert this bit in SCSI-2 systems so that a single bit error
on the SCSI bus is not interpreted as a single initiator
response.
R Reserved 3
TTM Timer Test Mode 2
Setting this bit facilitates testing of the selection time-out,
general purpose, and handshake-to-handshake timers by
greatly reducing all three time-out periods. Setting this bit
starts all three timers and if the respective bits in the
SCSI Interrupt Enable One (SIEN1) register are set, the
LSI53C810A generates interrupts at time-out. This bit is
intended for internal manufacturing diagnosis and should
not be used.
CSF Clear SCSI FIFO 1
Setting this bit causes the “full flags” for the SCSI FIFO
to be cleared. This empties the FIFO. This bit is
self-clearing. In addition to the SCSI FIFO pointers, the