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PCI Interface Timing Diagrams 7-15
Figure 7.11 Target Read
Data
Byte Enable
t
2
t
1
t
2
t
1
t
2
t
1
t
1
t
2
t
2
t
3
t
2
t
1
t
3
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD/
(Driven by Master-Addr;
C_BE/
(Driven by Master)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C810A)
STOP/
(Driven by LSI53C810A)
DEVSEL/
(Driven by LSI53C810A)
Out
t
3
In Out
t
3
LSI53C810A-Data)
LSI53C810A-Data)
CMD
t
3
Addr
In