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SCSI Input Data Latch (SIDL), SCSI Output Data Latch
(SODL), and SODR full bits in the SCSI Status Zero
(SSTAT0) register are cleared.
STW SCSI FIFO Test Write 0
Setting this bit places the SCSI core into a test mode in
which the FIFO is easily written. While this bit is set,
writes to the SCSI Output Data Latch (SODL) register
cause the entire word contained in this register to be
loaded into the FIFO. Writing the least significant byte of
the SCSI Output Data Latch (SODL) register causes the
FIFO to load.
Register: 0x50 (0xD0)
SCSI Input Data Latch (SIDL)
Read Only
SIDL SCSI Input Data Latch [15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the SCSI Output Data
Latch (SODL) register and then read back into the
LSI53C810A by reading this register to allow loopback
testing. When receiving SCSI data, the data flows into
this register and out to the host FIFO. This register differs
from the SCSI Bus Data Lines (SBDL) register; SCSI
Input Data Latch (SIDL) contains latched data and the
SCSI Bus Data Lines (SBDL) always contains exactly
what is currently on the SCSI data bus. Reading this
register causes the SCSI parity bit to be checked, and
causes a parity error interrupt if the data is not valid. The
power-up values are indeterminate.
15 0
SIDL
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