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CONTENTS
FIGURES
Figure Page
10-3 Source-Synchronized Transfers.................................................................................10-5
10-4 Destination-Synchronized Transfers ..........................................................................10-6
10-5 Two-Channel DMA Module ........................................................................................10-9
10-6 Examples of DMA Priority.........................................................................................10-10
10-7 DMA Source Pointer (High-Order Bits).....................................................................10-11
10-8 DMA Source Pointer (Low-Order Bits) .....................................................................10-12
10-9 DMA Destination Pointer (High-Order Bits)..............................................................10-13
10-10 DMA Destination Pointer (Low-Order Bits)...............................................................10-14
10-11 DMA Control Register...............................................................................................10-15
10-12 Transfer Count Register...........................................................................................10-19
11-1 80C187-Supported Data Types..................................................................................11-8
11-2 80C186 Modular Core Family/80C187 System Configuration....................................11-9
11-3 80C187 Configuration with a Partially Buffered Bus.................................................11-12
11-4 80C187 Exception Trapping via Processor Interrupt Pin..........................................11-14
12-1 Entering/Leaving ONCE Mode...................................................................................12-2
A-1 Formal Definition of ENTER........................................................................................A-3
A-2 Variable Access in Nested Procedures.......................................................................A-4
A-3 Stack Frame for Main at Level 1.................................................................................. A-4
A-4 Stack Frame for Procedure A at Level 2 ..................................................................... A-5
A-5 Stack Frame for Procedure B at Level 3 Called from A............................................... A-6
A-6 Stack Frame for Procedure C at Level 3 Called from B ..............................................A-7
B-1 Input Synchronization Circuit.......................................................................................B-1