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INTERRUPT CONTROL UNIT
8-22
Figure 8-13. End-of-Interrupt Register
8.4.8 Interrupt Status Register
The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer
interrupt. The CPU sets the DMA Halt bit to suspend DMA transfers while an NMI is processed.
Software can also read and write this bit. See “Suspension of DMA Transfers” on page 10-20 for
details. A timer bit is set to indicate a pending interrupt and is cleared when the interrupt request
is acknowledged. Any number of bits can be set at any one time.
Register Name: End-of-Interrupt Register
Register Mnemonic: EOI
Register Function: Used to issue an EOI command
Bit
Mnemonic
Bit Name
Reset
State
Function
NSPEC Nonspecific
EOI
0 Set to issue a nonspecific EOI.
VT4:0 Interrupt
Type
0 0000 Write with the interrupt type of the interrupt
whose In-Service bit is to be cleared.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
A1210-A0
15 0
V
T
0
V
T
2
V
T
3
V
T
4
N
S
P
E
C
V
T
1