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TIMER/COUNTER UNIT
Figure 9-6. Timer 2 Control Register
Register Name: Timer 2 Control Register
Register Mnemonic: T2CON
Register Function: Defines Timer 2 operation.
Bit
Mnemonic
Bit Name
Reset
State
Function
EN Enable 0 Set to enable the timer. This bit can be written
only when the INH
bit is set.
INH Inhibit X Set to enable writes to the EN bit. Clear to
ignore writes to the EN bit. The INH
bit is not
stored; it always reads as zero.
INT Interrupt X Set to generate an interrupt request when the
Count register equals a Maximum Count
register. Clear to disable interrupt requests.
MC Maximum
Count
X This bit is set when the counter reaches a
maximum count. The MC bit must be cleared
by writing to the Timer Control register. This
is not done automatically. If MC is clear, the
counter has not reached a maximum count.
CONT Continuous
Mode
X Set to cause the timer to run continuously.
Clear to disable the counter (clear the EN bit)
after each counting sequence.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
A1298-0A
15 0
C
O
N
T
M
C
I
N
T
I
N
H
E
N