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INDEX
Index-2
and chip-selects, 6-5
HALT state, exiting, 3-30
idle states, 3-18
instruction prefetch, 3-20
interrupt acknowledge (INTA) cycles, 3-6,
3-25–3-26, 8-9
and chip-selects, 6-5
interrupt acknowledge cycles, 8-29
operation, 3-7–3-20
priorities, 3-44–3-45, 7-2
read cycles, 3-20–3-21
refresh cycles, 3-22, 7-4, 7-5
control signals, 7-5, 7-6
during HOLD, 3-41–3-43, 7-12–7-13
wait states, 3-13–3-18
write cycles, 3-22–3-25
See also Data transfers
Bus hold protocol, 3-39–3-44
and CLKOUT, 5-6
and CSU, 6-18
and refresh cycles, 3-41–3-43, 7-12–7-13
and reset, 5-9
latency, 3-40–3-41
Bus Interface Unit (BIU), 2-1, 2-3, 2-11, 3-1–3-45
and DMA, 10-8
and DRAM refresh requests, 7-4
and TCU, 9-1
buffering the data bus, 3-34–3-36
modifying interface, 3-33–3-36, 3-36
relationship to RCU, 7-1
synchronizing software and hardware events,
3-36–3-37
using a locked bus, 3-37–3-38
using multiple bus masters, 3-39–3-44
using the queue status signals, 3-38–3-39
BX register, 2-1, 2-5, 2-30
C
Carry Flag (CF), 2-7, 2-9
Chip-Select Unit (CSU), 6-1
and DMA, 10-8
and DMA acknowledge signal, 10-22
and HALT bus cycles, 3-28
and READY, 6-15–6-16
and wait states, 6-15–6-16
block diagram, 6-3
bus cycle decoding, 6-17
examples, 6-18–6-22
features and benefits, 6-1
functional overview, 6-2–6-5
programming, 6-6–6-17
registers, 6-6–6-12
system diagram, 6-19
See also Chip selects
Chip-selects
activating, 6-5
and 80C187 interface, 6-17, 10-11
and bus hold protocol, 6-18
and DMA acknowledge signal, 10-22
and DRAM controllers, 7-1
and reserved I/O locations, 6-17
initializing, 6-6–6-18
methods for generating, 6-1
overlapping, 6-16–6-17
programming considerations, 6-17
start address, 6-17
timing, 6-4
CL register, 2-5, 2-21, 2-22
CLKOUT
and bus hold, 5-6
and power management modes, 5-6
and reset, 5-6
Clock divider, 5-11
control register, 5-12
Clock generator, 5-6–5-10
and system reset, 5-6–5-7
output, 5-6
synchronizing CLKOUT and RESOUT, 5-6–
5-7
Clock sources, TCU, 9-12
Code (programs)‚ See Software
Code segment, 2-5
CompuServe forums, 1-6
Counters‚ See Timer Counter Unit (TCU)
CPU, block diagram, 2-2
Crystal‚ See Oscillator
CS register, 2-1, 2-5, 2-6, 2-13, 2-23, 2-39, 2-41
Customer service, 1-4
CX register, 2-1, 2-5, 2-23, 2-25, 2-26
D
Data, 3-6
Data bus, See Address and data bus
Data segment, 2-5