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INTERRUPT CONTROL UNIT
8-14
.
Figure 8-5. Interrupt Control Register for Noncascadable External Pins
Register Name: Interrupt Control Register (non-cascadable pins)
Register Mnemonic: I2CON, I3CON
Register Function: Control register for the non-cascadable external
internal interrupt pins
Bit
Mnemonic
Bit Name
Reset
State
Function
LVL Level-trigger 0 Selects the interrupt triggering mode:
0 = edge triggering
1 = level triggering.
MSK Interrupt
Mask
1 Clear to enable interrupts from this source.
PM2:0 Priority
Level
111 Defines the priority level for this source.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
A1214-A0
15 0
P
M
0
P
M
1
P
M
2
M
S
K
L
V
L