Intel 80C186XL Computer Hardware User Manual


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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-30. Simultaneous NMI, Single Step and Maskable Interrupt
A1034-0A
NMI
Push PSW, CS, IP
Fetch Divide Error Vector
IRET
Divide
Timer Interrupt
Push PSW, CS, IP
Fetch Single Step Vector
Push PSW, CS, IP
Fetch Single Step Vector
IRET
Execute Single Step Service Routine
Execute Single Step
Service Routine
Push PSW, CS, IP
Fetch NMI Vector
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = 1
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = 0
Interrupt Enable Bit (IE) = 0
Trap Flag (TF) = ???
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
Interrupt Enable Bit (IE) = 1
Trap Flag (TF) = X
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