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CONTENTS
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6.4.5 Memory or I/O Bus Cycle Decoding ........................................................................6-17
6.4.6 Programming Considerations ..................................................................................6-17
6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-18
6.6 EXAMPLES ................................................................................................................. 6-18
6.6.1 Example 1: Typical System Configuration ..............................................................6-18
CHAPTER 7
REFRESH CONTROL UNIT
7.1 THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2 REFRESH CONTROL UNIT CAPABILITIES................................................................. 7-2
7.3 REFRESH CONTROL UNIT OPERATION.................................................................... 7-2
7.4 REFRESH ADDRESSES............................................................................................... 7-4
7.5 REFRESH BUS CYCLES.............................................................................................. 7-5
7.6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5
7.7 PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1 Calculating the Refresh Interval ................................................................................7-7
7.7.2 Refresh Control Unit Registers .................................................................................7-7
7.7.2.1 Refresh Base Address Register ......................................................................7-8
7.7.2.2 Refresh Clock Interval Register .......................................................................7-8
7.7.2.3 Refresh Control Register .................................................................................7-9
7.7.3 Programming Example ...........................................................................................7-10
7.8 REFRESH OPERATION AND BUS HOLD.................................................................. 7-12
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1
8.2 MASTER MODE............................................................................................................ 8-2
8.2.1 Generic Functions in Master Mode ...........................................................................8-2
8.2.1.1 Interrupt Masking .............................................................................................8-3
8.2.1.2 Interrupt Priority ...............................................................................................8-3
8.2.1.3 Interrupt Nesting ..............................................................................................8-4
8.3 FUNCTIONAL OPERATION IN MASTER MODE ......................................................... 8-5
8.3.1 Typical Interrupt Sequence .......................................................................................8-5
8.3.2 Priority Resolution .....................................................................................................8-5
8.3.2.1 Priority Resolution Example ............................................................................8-6
8.3.2.2 Interrupts That Share a Single Source ............................................................8-7
8.3.3 Cascading with External 8259As ..............................................................................8-7
8.3.3.1 Special Fully Nested Mode ..............................................................................8-8
8.3.4 Interrupt Acknowledge Sequence .............................................................................8-9
8.3.5 Polling .......................................................................................................................8-9
8.3.6 Edge and Level Triggering ......................................................................................8-10
8.3.7 Additional Latency and Response Time .................................................................8-10