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C-15
INSTRUCTION SET DESCRIPTIONS
HLT Halt:
HLT
Causes the CPU to enter the halt
state. The processor leaves the halt
state upon activation of the RESET
line, upon receipt of a non-maskable
interrupt request on NMI, or upon
receipt of a maskable interrupt request
on INTR (if interrupts are enabled).
Instruction Operands:
none
None AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
Table C-4. Instruction Set (Continued)
Name Description Operation
Flags
Affected
NOTE: The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
? the contents of the flag is undefined after the instruction is executed
the flag is updated after the instruction is executed