BUS INTERFACE UNIT
3-14
Figure 3-12. Data Phase Signal Relationships
AD15:0
Write
AD15:0
Read
S2:0
CLKOUT
T2
T3
or TW
T4
or TI
RD/ WR
1
4
2
3
5
6
7
Valid
Read Data
Valid Write Data
NOTES:
1. T
CLRL/CLWL,
T
CLOV
: Clock low to valid RD/WR active, write data valid.
2. T
CLSH
: Clock low to status inactive.
3. T
DVCL
: Data input valid to clock low.
4. T
CLRH/CLWH
: Clock valid to RD/WR inactive.
5. T
CLDX
: Data input HOLD from clock low.
6. T
WHDX
: Output data HOLD from WR high.
7. T
RHAV
: Bus no longer floating from RD high.