3-15
BUS INTERFACE UNIT
Figure 3-13. Typical Bus Cycle with Wait States
Figure 3-14. ARDY and SRDY Pin Block Diagram
ALE
S2:0
A19:16
AD15:0
READY
WR
CLKOUT
T1 T2 T3 TW TW T4
Valid
Address
Address Valid Write Data
A1040-0A
DQ
ARDY
BUS READY
CLKOUT
Rising
Edge
DQ
Falling
Edge
SRDY
A1041-0A