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REFRESH CONTROL UNIT
7-12
Example 7-1. Initializing the Refresh Control Unit (Continued)
7.8 REFRESH OPERATION AND BUS HOLD
When another bus master controls the bus, the processor keeps HLDA
active as long as the
HOLD input remains active. If the Refresh Control Unit generates a refresh request during bus
hold, the processor drives the HLDA
signal inactive, indicating to the current bus master that it
wishes to regain bus control (see Figure 7-9). The BIU begins a refresh bus cycle only after the
alternate master removes HOLD. The user must design the system so that the processor can re-
gain bus control. If the alternate master asserts HOLD after the processor starts the refresh cycle,
the CPU will relinquish control by asserting HLDA
when the refresh cycle is complete.
mov dx, RFBASE ;set upper 7 address bits
mov ax, _dram_addr
out dx, al
mov dx, RFTIME ;set clock pre_scaler
mov ax, _clock_time
out dx, al
mov dx, RFCON ;Enable RCU
mov ax, Enable
out dx, al
mov cx, 8 ;8 dummy cycles are
;required by DRAMs
xor di, di ;before actual use
_exercise_ram:
mov word ptr [di], 0
loop _exercise_ram
pop di ;restore saved registers
pop dx
pop cx
pop ax
pop bp ;restore caller’s bp
ret
_config_rcu endp
lib_80186 ends
end