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PCI Configuration Registers 4-15
Register: 0x40
Capability ID
Read Only
CID Cap_ID [7:0]
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure.
Register: 0x41
Next Item Pointer
Read Only
NIP Next_Item_Ptr [7:0]
Bits [7:0] contain the offset location of the next item in the
controller’s capabilities list. The LSI53C875A has these
bits set to zero indicating no further extended capabilities
registers exist.
Registers:0x42–0x43
Power Management Capabilities (PMC)
Read Only
PMES PME_Support [15:11]
Bits [15:11] define the power management states in
which the LSI53C875A will assert the PME pin. These
bits are all set to zero because the LSI53C875A does not
provide a PME signal.
7 0
CID
00000001
7 0
NIP
00000000
15 11 10 9 8 6 5 4 3 2 0
PMES D2S D1S
R DSI APS PMEC VER[2:0]
00000 1 1
x x x00 0 010