Filter
Top Products
4-62 Registers
BO[9:8] DMA FIFO Byte Offset Counter, Bits [9:8] [1:0]
These are the upper two bits of the DFBOC. The DFBOC
consists of these bits, and the DMA FIFO (DFIFO)
register, bits [7:0].
Register: 0x23
Chip Test Six (CTEST6)
Read/Write
DF DMA FIFO [7:0]
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO as determined by the FBL bits in
the Chip Test Four (CTEST4) register. Reading this
register unloads data from the appropriate byte lane of
the DMA FIFO as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is loaded into
the top of the FIFO. Data read out of the FIFO is taken
from the bottom. To prevent DMA data from being
corrupted, this register should not be accessed before
starting or restarting SCRIPTS operation. Write this
register only when testing the DMA FIFO using the
CTEST4 register. Writing to this register while the test
mode is not enabled produces unexpected results.
Registers:0x24–0x26
DMA Byte Counter (DBC)
Read/Write
DBC DMA Byte Counter [23:0]
This 24-bit register determines the number of bytes
transferred in a Block Move instruction. While sending
data to the SCSI bus, the counter is decremented as data
is moved into the DMA FIFO from memory. While
receiving data from the SCSI bus, the counter is
decremented as data is written to memory from the
7 0
DF
00000000
23 0
DBC
xxxxxxxxxxxxxxxxxxxxxxxx