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4-96 Registers
ENNDJ Enable Jump on Nondata Phase Mismatches 5
This bit controls whether or not a jump is taken during a
nondata phase mismatch (i.e. message in, message out,
status, or command). When this bit is clear, jumps will
only be taken on Data-In or Data-Out phases and a
phase mismatch interrupt will be generated for all other
phases. When this bit is set, jumps will be taken
regardless of the phase in the block move. Note that the
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
DISFC Disable Auto FIFO Clear 4
This bit controls whether or not the FIFO is automatically
cleared during a Data-Out phase mismatch. When set,
data in the DMA FIFO as well as data in the SCSI Output
Data Latch (SODL) and SODR, a hidden buffer register
which is not accessible, will not be cleared after
calculations on them are complete. When cleared, the
DMA FIFO and SODL and SODR will automatically be
cleared. This bit also disables the enhanced flushing
mechanism.
R Reserved [3:2]
DILS Disable Internal Load and Store 1
This bit controls whether or not Load and Store data
transfers in which the source/destination is located in
SCRIPTS RAM generate external PCI cycles.
If cleared, Load and Store data transfers of this type will
NOT generate PCI cycles, but will stay internal to the
chip.
If set, Load and Store data transfers of this type will
generate PCI cycles.
R Reserved 0