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5-10 SCSI SCRIPTS Instruction Set
register contains 0x000000, an illegal instruction
interrupt is generated.
4. The LSI53C875A transfers the number of bytes specified in
the DBC register starting at the address specified in the
DMA Next Address (DNAD) register. If the OpCode bit is
set and a data transfer ends on an odd byte boundary, the
LSI53C875A stores the last byte in the SCSI Wide Residue
(SWIDE) register during a receive operation. This byte is
combined with the first byte from the subsequent transfer
so that a wide transfer can be completed.
5. If the SATN/ signal is asserted by the Initiator or a parity
error occurred during the transfer, the transfer can
optionally be halted and an interrupt generated. The
Disable Halt on Parity Error or ATN bit in the SCSI Control
One (SCNTL1) register controls whether the LSI53C875A
halts on these conditions immediately, or waits until
completion of the current Move.
Initiator Mode
In Target mode, the OpCode bit defines the following
operations:
These instructions perform the following steps:
1. The LSI53C875A verifies that it is connected to the SCSI
bus as an Initiator before executing this instruction.
2. The LSI53C875A waits for an unserviced phase to occur.
An unserviced phase is any phase (with SREQ/ asserted)
for which the LSI53C875A has not yet transferred data by
responding with a SACK/.
3. The LSI53C875A compares the SCSI phase bits in the
DMA Command (DCMD) register with the latched SCSI
phase lines stored in the SCSI Status One (SSTAT1)
OPC Instruction Defined
0CHMOV
1MOVE