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4-72 Registers
STD Start DMA Operation 2
The LSI53C875A fetches a SCSI SCRIPTS instruction
from the address contained in the DMA SCRIPTS Pointer
(DSP) register when this bit is set. This bit is required if
the LSI53C875A is in one of the following modes:
• Manualstartmode–Bit0intheDMA Mode
(DMODE) register is set
• Singlestepmode–Bit4intheDMA Control (DCNTL)
register is set
When the LSI53C875A is executing SCRIPTS in manual
start mode, the Start DMA bit must be set to start
instruction fetches, but need not be set again until an
interrupt occurs. When the LSI53C875A is in single step
mode, set the Start DMA bit to restart execution of
SCRIPTS after a single step interrupt.
IRQD IRQ Disable 1
Setting this bit disables the IRQ pin. Clearing the bit
enables normal operation. As with any other register
other than Interrupt Status Zero (ISTAT0) and Interrupt
Status One (ISTAT1), this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS
execution. For more information on the use of this bit in
interrupt handling, see Chapter 2, “Functional
Description.”
COM LSI53C700 Compatibility 0
When the COM bit is cleared, the LSI53C875A behaves
in a manner compatible with the LSI53C700;
selection/reselection IDs are stored in both the SCSI
Selector ID (SSID) and SCSI First Byte Received (SFBR)
registers. This bit is not affected by a software reset.
If the COM bit is cleared, do not access this register
using SCRIPTS operation as nondeterminate operations
may occur. (This includes SCRIPTS Read/Write
operations and conditional transfer control instructions
that initialize the SFBR register.)
When the COM bit is set, the ID is stored only in the
SSID register, protecting the SFBR from being
overwritten if a selection/reselection occurs during a DMA
register-to-register operation.