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viii Contents
2.2.11 Parity Options 2-24
2.2.12 DMA FIFO 2-27
2.2.13 SCSI Bus Interface 2-32
2.2.14 Select/Reselect During Selection/Reselection 2-33
2.2.15 Synchronous Operation 2-34
2.2.16 Interrupt Handling 2-37
2.2.17 Chained Block Moves 2-44
2.3 Parallel ROM Interface 2-48
2.4 Serial EEPROM Interface 2-50
2.4.1 Default Download Mode 2-50
2.4.2 No Download Mode 2-51
2.5 Power Management 2-51
2.5.1 Power State D0 2-52
2.5.2 Power State D1 2-52
2.5.3 Power State D2 2-53
2.5.4 Power State D3 2-53
Chapter 3 Signal Descriptions
3.1 LSI53C875A Functional Signal Grouping 3-2
3.2 Signal Descriptions 3-3
3.2.1 Internal Pull-ups on LSI53C875A Signals 3-3
3.3 PCI Bus Interface Signals 3-4
3.3.1 System Signals 3-4
3.3.2 Address and Data Signals 3-5
3.3.3 Interface Control Signals 3-6
3.3.4 Arbitration Signals 3-7
3.3.5 Error Reporting Signals 3-7
3.3.6 Interrupt Signal 3-8
3.4 SCSI Bus Interface Signals 3-8
3.4.1 SCSI Bus Interface Signal 3-8
3.4.2 SCSI Signals 3-9
3.4.3 SCSI Control Signals 3-9
3.5 GPIO Signals 3-10
3.6 ROM Flash and Memory Interface Signals 3-11
3.7 Test Interface Signals 3-12
3.8 Power and Ground Signals 3-13
3.9 MAD Bus Programming 3-14