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2-22 Functional Description
• On every Store instruction. The Store instruction may also be used
to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.
• On every write to the DMA SCRIPTS Pointer (DSP) register.
• On all Transfer Control instructions when the transfer conditions are
met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.
• WhenthePrefetchFlushbit(DMA Control (DCNTL) register, bit 6)
is set. The unit flushes whenever this bit is set. The bit is self-
clearing.
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode
(DMODE) register (0x38) causes the LSI53C875A to burst in the first two
Dwords of all instruction fetches. If the instruction is a Memory-to-
Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.
Note:
This feature is only useful if Prefetching is disabled and
SCRIPTS instructions are fetched from main memory. Due
to the short SCRIPTS RAM access time, burst opcode
fetching is not necessary when fetching instructions from
this memory.
2.2.8 Load and Store Instructions
The LSI53C875A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the Data Structure Address (DSA) register. Load and Store data
transfers to or from the SCRIPTS RAM will remain internal to the chip
and will not generate PCI bus cycles. While a Load/Store to or from
SCRIPTS RAM is occurring, any external PCI slave cycles that occur are
retried on the PCI bus. This feature can be disabled by setting the DILS
bit in the Chip Control 0 (CCNTL0) register. For more information on the