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SCSI Registers 4-45
SDP0L Latched SCSI Parity 3
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the SCSI Input Data
Latch (SIDL). It changes when a new byte is latched into
the least significant byte of the SIDL register. This bit is
active HIGH, in other words, it is set when the parity
signal is active.
MSG SCSIMSG/Signal 2
C_D SCSIC_D/Signal 1
I_O SCSII_O/Signal 0
These three SCSI phase status bits (MSG, C_D, and
I_O) are latched on the asserting edge of SREQ/ when
operating in either the initiator or target mode. These bits
are set when the corresponding signal is active. They are
useful when operating in the low level mode.
1 0011 19
1 0100 20
1 0101 21
1 0110 22
1 0111 23
1 1000 24
1 1001 25
1 1010 26
1 1011 27
1 1100 28
1 1101 29
1 1110 30
1 1111 31
Table 4.6 SCSI Synchronous Data FIFO Word Count (Cont.)
FF4
(SSTAT2 bit 4) FF3 FF2 FF1 FF0
Bytes or Words
in the
SCSI FIFO