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2-4 Functional Description
2.1.2.1 Interrupt Acknowledge Command
The LSI53C875A does not respond to this command as a slave and it
never generates this command as a master.
2.1.2.2 Special Cycle Command
The LSI53C875A does not respond to this command as a slave and it
never generates this command as a master.
Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A
C_BE[3:0]/ Command Type Supported as Master Supported as Slave
0b0000 Interrupt Acknowledge No No
0b0001 Special Cycle No No
0b0010 I/O Read Yes Yes
0b0011 I/O Write Yes Yes
0b0100 Reserved n/a n/a
0b0101 Reserved n/a n/a
0b0110 Memory Read Yes Yes
0b0111 Memory Write Yes Yes
0b1000 Reserved n/a n/a
0b1001 Reserved n/a n/a
0b1010 Configuration Read No Yes
0b1011 Configuration Write No Yes
0b1100 Memory Read Multiple Yes
1
1. See the DMA Mode (DMODE) register.
Yes (defaults to 0b0110)
0b1101 Dual Address Cycle (DAC) Yes No
0b1110 Memory Read Line Yes
1
Yes (defaults to 0b0110)
0b1111 Memory Write and Invalidate Yes
2
2. See the Chip Test Three (CTEST3) register.
Yes (defaults to 0b0111)