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Block Move Instruction 5-11
register. These phase lines are latched when SREQ/ is
asserted.
4. IftheSCSIphasebitsmatchthevaluestoredintheSCSI
SCSI Status One (SSTAT1) register, the LSI53C875A
transfers the number of bytes specified in the DMA Byte
Counter (DBC) register starting at the address pointed to
by the DMA Next Address (DNAD) register. If the OpCode
bit is cleared and a data transfer ends on an odd byte
boundary, the LSI53C875A stores the last byte in the SCSI
Wide Residue (SWIDE) register during a receive operation,
or in the SCSI Output Data Latch (SODL) register during a
send operation. This byte is combined with the first byte
from the subsequent transfer so that a wide transfer can
complete.
5. If the SCSI phase bits do not match the value stored in the
SCSI Status One (SSTAT1) register, the LSI53C875A
generates a phase mismatch interrupt and the instruction is
not executed.
6. During a Message-Out phase, after the LSI53C875A has
performed a select with Attention (or SATN/ is manually
asserted with a Set ATN instruction), the LSI53C875A
deasserts SATN/ during the final SREQ/SACK/ handshake.
7. When the LSI53C875A is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the SACK/
signal using the Clear SACK I/O instruction.
SCSIP[2:0] SCSI Phase [26:24]
This 3-bit field defines the SCSI information transfer
phase. When the LSI53C875A operates in Initiator mode,
these bits are compared with the latched SCSI phase bits
in the SCSI Status One (SSTAT1) register. When the
LSI53C875A operates in Target mode, it asserts the
phase defined in this field. Table 5.2 describes the
possible combinations and the corresponding SCSI
phase.