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4-24 Registers
may transfer up to three additional bytes before halting to
synchronize between internal core cells. During
synchronous operation, the LSI53C875A transfers data
until there are no outstanding synchronous offsets. If the
LSI53C875A is receiving data, any data residing in the
DMA FIFO is sent to memory before halting.
When this bit is set, the LSI53C875A does not halt the
SCSI transfer when SATN/ or a parity error is received.
CON Connected 4
This bit is automatically set any time the LSI53C875A is
connected to the SCSI bus as an initiator or as a target.
It is set after the LSI53C875A successfully completes
arbitration or when it has responded to a bus initiated
selection or reselection. This bit is also set after the chip
wins simple arbitration when operating in low level mode.
When this bit is cleared, the LSI53C875A is not
connected to the SCSI bus.
The CPU can force a connected or disconnected
condition by setting or clearing this bit. This feature is
used primarily during loopback mode.
RST Assert SCSI RST/ Signal 3
Setting this bit asserts the SRST/ signal. The SRST/
output remains asserted until this bit is cleared. The
25
=µs minimum assertion time defined in the SCSI
specification must be timed out by the controlling
microprocessor or a SCRIPTS loop.
AESP Assert Even SCSI Parity (force bad parity) 2
When this bit is set, the LSI53C875A asserts even parity.
It forces a SCSI parity error on each byte sent to the
SCSI bus from the chip. If parity checking is enabled,
then the LSI53C875A checks data received for odd parity.
This bit is used for diagnostic testing and is cleared for
normal operation. It is useful to generate parity errors to
test error handling functions.
IARB Immediate Arbitration 1
Setting this bit causes the SCSI core to immediately
begin arbitration once a Bus Free phase is detected
following an expected SCSI disconnect. This bit is useful
for multithreaded applications. The ARB[1:0] bits in the