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4-76 Registers
HTH Handshake-to-Handshake Timer Expired 0
The handshake-to-handshake timer is expired. The time
measured is the SCSI Request-to-Request (target) or
Acknowledge-to-Acknowledge (initiator) period. See the
description of the SCSI Timer Zero (STIME0) register,
bits [7:4], for more information on the handshake-
to-handshake timer.
Register: 0x42
SCSI Interrupt Status Zero (SIST0)
Read Only
Reading the SIST0 register returns the status of the various interrupt
conditions, whether they are enabled in the SCSI Interrupt Enable Zero
(SIEN0) register or not. Each bit set indicates occurrence of the
corresponding condition. Reading the SIST0 clears the interrupt status.
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending (the LSI53C875A stacks interrupts). SCSI
interrupt conditions are individually masked through the SCSI Interrupt
Enable Zero (SIEN0) register.
When performing consecutive 8-bit reads of the DMA Status (DSTAT),
SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One
(SIST1) registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the Interrupt Status Zero (ISTAT0) SIP
and DIP bits may not be set, read the SIST0 and SIST1 registers before
the DSTAT register to avoid missing a SCSI interrupt. For more
information on interrupts, refer to Chapter 2, “Functional Description.”
M/A Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active 7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
76543210
M/A CMP SEL RSL SGE UDC RST PAR
00000000