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3-6 Signal Descriptions
3.3.3 Interface Control Signals
Table 3.4 describes the Interface Control signals.
Table 3.4 Interface Control Signals
Name PQFP BGA Type Strength Description
FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate
the beginning and duration of an access. FRAME/ is
asserted to indicate that a bus transaction is beginning.
While FRAME/ is deasserted, either the transaction is
in the final data phase or the bus is idle.
TRDY/ 19 G3 S/T/S 8 mA PCI Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of
the transaction. TRDY/ is used with IRDY/. A data
phase is completed on any clock when used with
IRDY/. A data phase is completed on any clock when
both TRDY/ and IRDY/ are sampled asserted. During a
read, TRDY/ indicates that valid data is present on
AD[31:0]. During a write, it indicates that the target is
prepared to accept data. Wait cycles are inserted until
both IRDY/ and TRDY/ are asserted together.
IRDY/ 17 F1 S/T/S 8 mA PCI Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of
the transaction. IRDY/ is used with TRDY/. A data
phase is completed on any clock when both IRDY/ and
TRDY/ are sampled asserted. During a write, IRDY/
indicates that valid data is present on AD[31:0]. During
a read, it indicates that the master is prepared to
accept data. Wait cycles are inserted until both IRDY/
and TRDY/ are asserted together.
STOP/ 22 G4 S/T/S 8 mA PCI Stop indicates that the selected target is requesting
the master to stop the current transaction.
DEVSEL/ 20 G2 S/T/S 8 mA PCI Device Select indicates that the driving device has
decoded its address as the target of the current
access. As an input, it indicates to a master whether
any device on the bus has been selected.
IDSEL 2 B1 I N/A Initialization Device Select is used as a chip select in
place of the upper 24 address lines during
configuration read and write transactions.