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Phase Mismatch Jump Registers 4-107
Registers:0xD4–0xD7
Instruction Address (IA)
Read/Write
IA Instruction Address [31:0]
This register always contains the address of the BMOV
instruction that was executing when the phase mismatch
occurred. This value will always match the value in the
Entry Storage Address (ESA) except in the case of a
table indirect BMOV in which case the ESA will have the
address of the table indirect entry and this register will
point to the address of the BMOV instruction.
Registers:0xD8–0xDA
SCSI Byte Count (SBC)
Read Only
SBC SCSI Byte Count [23:0]
This register contains the count of the number of bytes
transferred to or from the SCSI bus during any given
BMOV. This value is used in calculating the information
placed into the Remaining Byte Count (RBC) and
Updated Address (UA) register and should not need to be
used in normal operations. There are two conditions in
which this byte count will not match the number of bytes
transferred exactly. If a BMOV is executed to transfer an
odd number of bytes across a wide bus then the byte
count at the end of the BMOV will be greater than the
number of bytes sent by one. This will also happen in an
odd byte count wide receive case. Also, in the case of a
wide send in which there is a chain byte from a previous
transfer, the count will not reflect the chain byte sent
across the bus during that BMOV. The reason for this is
due to the fact that to determine the correct address to
start fetching data from after a phase mismatch this byte
31 0
IA
00000000000000000000000000000000
23 0
SBC
000000000000000000000000